Memory cell with polysilicon local interconnects

ABSTRACT

Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.

RELATED APPLICATION

This Application is a Divisional of U.S. application Ser. No.10/714,752, titled “METHOD FOR FORMING POLYSILICON LOCAL INTERCONNECTS,”filed Nov. 17, 2003, (pending) which is commonly assigned andincorporated herein by reference.

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to integrated circuit devicesand, in particular, to the formation of local polysilicon interconnectsfor a semiconductor memory device.

BACKGROUND OF THE INVENTION

Memory devices are typically provided as internal storage areas in thecomputer. The term memory identifies data storage that comes in the formof integrated circuit chips. In general, memory devices contain an arrayof memory cells for storing data, and row and column decoder circuitscoupled to the array of memory cells for accessing the array of memorycells in response to an external address.

There are several different types of memory used in modem electronics,one common type is RAM (random-access memory). RAM is characteristicallyfound in use as main memory in a computer environment. RAM refers toread and write memory; that is, you can both write data into RAM andread data from RAM. This is in contrast to read-only memory (ROM), whichpermits you only to read data. Most RAM is volatile, which means that itrequires a steady flow of electricity to maintain its contents. As soonas the power is turned off, whatever data was in RAM is lost.

One other type of non-volatile memory is known as Flash memory. A flashmemory is a type of EEPROM (electrically-erasable programmable read-onlymemory) that can be erased and reprogrammed in blocks. Many modempersonal computers (PCs) have their BIOS stored on a flash memory chipso that it can easily be updated if necessary. Such a BIOS is sometimescalled a flash BIOS. Flash memory is also popular in wireless electronicdevices because it enables the manufacturer to support new communicationprotocols as they become standardized and to provide the ability toremotely upgrade the device for enhanced features.

A typical flash memory comprises a memory array that includes a largenumber of memory cells arranged in row and column fashion. Each of thememory cells includes a floating-gate field-effect transistor capable ofholding a charge. The cells are usually grouped into blocks. Each of thecells within a block can be electrically programmed in a random basis bycharging the floating gate. The charge can be removed from the floatinggate by a block erase operation. The data in a cell is determined by thepresence or absence of the charge in the floating gate.

Flash memory typically utilizes one of two basic architectures known asNOR flash and NAND flash. The designation is derived from the logic usedto read the devices. In NOR flash architecture, a column of memory cellsare coupled in parallel with each memory cell coupled to a bit line. InNAND flash architecture, a column of memory cells are coupled in serieswith only the first memory cell of the column coupled to a bit line.

Memory device fabricators are continuously seeking to reduce the size ofthe devices. Smaller devices facilitate higher productivity and reducedpower consumption. However, as device sizes become smaller, the sizes ofvarious standard features become increasingly important. This is true inparticular for semiconductor memory arrays where a small decrease insize of a feature can be magnified by being repeated throughout thearray. One such repeated feature in memory arrays are local interconnectlines that can couple the local source, drains, and/or control gates ofmemory cells to the larger global source supply lines, bit lines, andword lines of the memory array. Two common manners for forming theselocal interconnect lines are depositing a line of polysilicon, metal, orsimilar conducting material into an insulated trench or diffusing adopant into a substrate to form a conducting line. However, both ofthese approaches have exhibited issues that make them problematic intheir reducing feature size; local interconnect lines formed ofpolysilicon or metal are often difficult and expensive to process inincreasingly narrow trench areas and diffusing enough dopant to form aconduction line of a sufficiently low resistance can form deep and broadregion junction areas that make it difficult to shrink the cell gatearea.

For the reasons stated above, and for other reasons stated below whichwill become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art foralternate methods and circuits for providing local interconnectconnections to portions of a semiconductor memory device.

SUMMARY OF THE INVENTION

The above-mentioned problems with memory devices and other problems areaddressed by the present invention and will be understood by reading andstudying the following specification.

Various embodiments of the invention facilitate forming of lowresistance polysilicon local interconnects that allow a smaller arrayfeature size and therefore facilitate forming arrays of a denser arrayformat. Embodiments of the present invention are formed utilizing a wetetch process that has a high selectivity, allowing the deposition andetching of polysilicon local interconnects to source and drain regionsof array transistors. In addition, by forming local interconnects andcontacts to the source regions of array elements with a high selectivityetch the size of the area dedicated to each interconnect line isreduced, thus allowing the use of a smaller pitch, i.e., a smallerspacing between adjacent word lines. By providing for a localinterconnect of polysilicon, a smaller source region and/or drain regioncan also be utilized, further decreasing the required word line spacing.Low resistance polysilicon local source interconnects can also couple toan increased number of memory cells, thereby reducing the number ofcontacts made to an array ground.

For one embodiment, the invention provides a method of fabricating asource interconnect to a memory cell comprising forming a layer ofdielectric material overlying a gate stack, a source region and a drainregion of the memory cell, forming a first mask layer overlying thelayer of dielectric material, patterning the first mask layer to exposea portion of the layer of dielectric material over at least the sourceregion, removing a portion of the exposed portion of the layer ofdielectric material to expose the source region, removing the first masklayer, forming a layer of polysilicon overlying the layer of dielectricmaterial and in contact with the exposed source region, forming a secondmask layer overlying the layer of polysilicon, patterning the secondmask layer to expose a portion of the layer of polysilicon over at leastthe source region, implanting ions in the exposed portion of the layerof polysilicon, thereby forming an implanted portion of the layer ofpolysilicon and an non-implanted portion of the layer of polysilicon,removing the second mask layer, and selectively etching the layer ofpolysilicon to preferentially remove the non-implanted portion, therebyforming the source interconnect.

For another embodiment, the invention provides a method of fabricating alocal interconnect comprising forming a dielectric layer having one ormore trenches formed in it, depositing a layer of silicon-containingmaterial over the dielectric layer, selectively implanting ions in oneor more regions of the layer of silicon-containing material over the oneor more trenches, and wet etching the layer of silicon-containingmaterial to remove the non-implanted regions of the layer ofsilicon-containing material to form one or more local interconnect linesin the one or more trenches.

For yet another embodiment, the invention provides a method offabricating a memory cell comprising forming a memory cell having asource and a source region and a drain region, and forming a localinterconnect of polysilicon to contact to the source and/or drain regionof the memory cell. Wherein forming a local interconnect of polysiliconcomprises the steps of forming a dielectric layer over the memory cellhaving at least one contact hole to the source/drain region of thememory cell, depositing a layer of polysilicon overlying the dielectriclayer to contact the source and/or drain region of the memory cellthrough the at least one contact hole of the dielectric layer,selectively implanting ions in one or more selected regions of the layerof polysilicon, and wet etching the layer of polysilicon to remove thenon-implanted regions of the layer of polysilicon to form at least onepolysilicon contact from the selected regions of the layer ofpolysilicon.

For a further embodiment, the invention provides a memory devicecomprising an array of floating-gate memory cells. The array offloating-gate memory cells comprising a plurality of rows of memorycells, each row coupled to a word line, a plurality of columns of memorycells, each column coupled to a bit line, a plurality of array sourceinterconnects, each interconnect coupled to source regions of at least aportion of a row of memory cells, and a plurality of drain contacts,each drain contact coupled between a drain region of a memory cell and abit line, wherein each array source interconnect comprises a polysiliconlayer with an ion implanted top layer, where each array sourceinterconnect is in contact with its associated source regions.

The invention further provides methods and apparatus of varying scope.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are cross-sectional views of a portion of a memory arrayof the prior art.

FIGS. 2A-2G are cross-sectional views of a portion of a memory arrayduring various stages of fabrication in accordance with an embodiment ofthe invention.

FIG. 3 is a schematic of a portion of a non-volatile memory array inaccordance with an embodiment of the invention.

FIG. 4 is a functional block diagram of a basic flash memory device inaccordance with an embodiment of the invention coupled to a processor.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description of the preferred embodiments,reference is made to the accompanying drawings that form a part hereof,and in which is shown by way of illustration specific embodiments inwhich the inventions may be practiced. These embodiments are describedin sufficient detail to enable those skilled in the art to practice theinvention, and it is to be understood that other embodiments may beutilized and that process or mechanical changes may be made withoutdeparting from the scope of the present invention. The terms wafer andsubstrate used previously and in the following description include anybase semiconductor structure. Both are to be understood as includingsilicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI)technology, thin film transistor (TFT) technology, doped and undopedsemiconductors, epitaxial layers of silicon supported by a basesemiconductor, as well as other semiconductor structures well known toone skilled in the art. Furthermore, when reference is made to a waferor substrate in the following description, previous process steps mayhave been utilized to form regions/junctions in the base semiconductorstructure. The following detailed description is, therefore, not to betaken in a limiting sense, and the scope of the present invention isdefined only by the appended claims and their equivalents.

Embodiments of the present invention facilitate forming of lowresistance polysilicon local interconnects that allow a smaller arrayfeature size and therefore facilitate forming arrays of a denser arrayformat. Memory devices and other integrated devices of the presentinvention are formed utilizing a wet etch process that has a highselectivity, allowing the deposition and etching of polysilicon localinterconnects to source regions of array transistors. In addition, byforming local interconnects and contacts to the drain and source regionsof array elements with a high selectivity etch, the size of the areadedicated to each interconnect line is reduced, thus allowing the use ofa smaller pitch, i.e., a smaller spacing between adjacent word lines ormemory cells. By providing for a local interconnect of polysilicon, asmaller source region and/or drain region can also be utilized, furtherdecreasing the required word line spacing. Low resistance polysiliconlocal source interconnects can also couple to an increased number ofmemory cells, thereby reducing the number of contacts made to an arrayground.

FIGS. 1A and 1B generally depict a simplified flash memory floating gatearray of the prior art. Formation of the structure depicted in FIG. 1Ais well known and will not be detailed herein. In general, FIG. 1Adepicts several gate stacks 145 of layers that will form word lines ofthe memory array. The gate stacks 145 include a first conductive layer115 is formed isolated in a dielectric 165 to form a floating gate. Asecond conductive layer 125 is formed overlying the first conductivelayer 115 to form a control gate. The layers are patterned into stacks145, as shown in FIG. 1A, and drain regions 135 and source regions 140are formed in the substrate 105, such as by implantation or diffusion ofdopant materials. In FIG. 1A, the flash memory array utilizes a sourceregion 140 that has been deeply diffused into the substrate 105 to lowerthe source resistance and allow it to function as a source localinterconnect. In FIG. 1 A, a bit line 150 has been formed and bit linecontacts 155 couple the bit line 150 to the drain regions 135 of thearray. As detailed in FIG. 1A, the deep diffusion of the source region140 to gain lower resistance levels has the undesirable effect ofbroadening the width of the source region 140, making it difficult toshrink the memory cell gate length and limiting the amount the array maybe reduced in word line pitch size.

FIG. 1B depicts another flash memory array of the prior art thatutilizes a local interconnect 160 that has been formed between the wordline stacks 145 to contact the array source region 140 and function as asource local interconnect. In FIG. 1B, as with FIG. 1A, a bit line 150has been formed and bit line contacts 155 couple the bit line 150 to thedrain regions 135 of the array. The local source interconnects 160 ofFIG. 1B are typically formed by a standard process method in which,after patterning the word line stacks 145 and depositing the insulatinglayer 165, a dry etch is utilized to form a trench or contact hole inthe insulating layer 165 on the array source region 140. The trench orcontact hole is then filled with doped polysilicon or metal. A problemwith this is that the typical dry etch utilized against the insulatinglayer 165 does not have very good selectivity against the portion of theinsulator 165 used to form the sidewalls and cap layer of the word linestacks 145 (not shown) and can dangerously thin them. As the cap layerand sidewall dielectric insulates the source local interconnect supplyline 160 from the word line stack 145, if it is too thin it can breakdown when erase voltages (which can be as high as 16v-20v) are appliedto the array, causing failure of the memory device. As a result, aninsulting cap layer and the insulating sidewalls of the word line stacks145 are over-designed to avoid this problem. As detailed in FIG. 1B, thelocal interconnects 160 and their insulating sidewalls and cap layerslimit the amount the array may be reduced in word line pitch sizewithout reducing the critical insulation separation of the interconnect160 and the adjacent word line stacks 145. The additional insulationlayer margin has the effect of limiting the amount of word line pitchreductions to avoid dangerously thinning the insulation layer 165between the word line stacks 145 and the deposited interconnects 160.

In particular, the relatively low selectivity of the dry etch processcan thin the insulating layer 165 at the top corners of the word linestack 145. Therefore, dry etch processes typically utilize a largerinsulating layer 165 than electrically required to provide additionalmargin for the dry etch process and help avoid electrical break through.In addition, the complexity and cost of dry etch process is increased.This difficult local polysilicon formation process tends to increasefail rates in the completed memory arrays and decreases the resultingmanufacturer's processing yield rates.

A wet etch process has been disclosed that allows polysilicon to beselectively etched between implanted and non-implanted regions. This wetetch process is detailed in U.S. Pat. No. 6,309,975, titled “Methods ofmaking implanted structures”, issued Oct. 30, 2001, which is commonlyassigned. This wet etch method of polysilicon is not anisotropic and hasa high etch selectivity allowing it to be advantageously used inembodiments of the present invention.

In general, the wet etch process operates by depositing a layer ofsilicon-containing material (such as polysilicon), masking it with apatterned resist layer, and then implanting the exposed areas of thesilicon-containing material with ions to a selected threshold dosagelevel. After implanting the ions, the resist layer is stripped and thesilicon-containing material is then wet etched to remove the excessmaterial. One such chemical that can be utilized for the wet etch isdilute TMAH (tetramethyl ammonium hydroxide). The etch rate of theimplanted regions of the silicon-containing material during the wet etchwill be lower than the un-implanted regions, thus the silicon-containingmaterial can be etched away from the un-implanted regions with a highrate of selectivity. In an alternative embodiment, a wet etchant isutilized that etches the implanted regions silicon-containing materialat a higher rate than the un-implanted regions.

In the wet etch process a layer of silicon-containing material, which inone embodiment comprises polysilicon, is provided. A masking layer isformed on the layer of silicon-containing material that masks at leastone region of the layer of silicon-containing material and leaves asecond region of the layer of silicon-containing material unmasked.

Ions of a selected type are then implanted into the unmasked portion ofthe layer of silicon-containing material. The ions are of a type that isselected in accordance with an etching process which is selective toimplanted silicon-containing material in a manner which will hereafterbe discussed. In order to reduce the dimensions of the selected patternfrom the dimensions of the masking layer, the ions can be implanted withan angle of implantation other than orthogonal to the semiconductorsubstrate, causing the ions to be implanted under the edges of themasking layer. Implanting the ions with an angle of implantation otherthan orthogonal to the semiconductor substrate will result in areduction in the dimensions of the selected patterns from the dimensionsof the masking layer, while an angle of implantation orthogonal to thesurface of the semiconductor substrate results in no substantialdimension change. Other ion implantation parameters, such as ion type,implantation dose, and implantation energy can also be appropriatelyselected to further tailor the dimensions of the implanted region andthereby the resulting etched shape. The impermeability to ions of theselected masking material also has an effect in sculpting the resultingshaped structure. Diffusing the ions after ion implantation with a heattreatment deepens the penetration of the ions into the polysilicon layerand further serves to tailor the profile of the resultant shapedfeature, though it is generally preferred not to heat treat in order tomaintain a sharper profile of the implanted ions in the layer ofsilicon-containing material.

Additionally, in order to vary the dimensions in a uniform manner, theion implantation operation can be conducted in multiple implantationstages with one ion implantation parameter being varied for eachimplantation stage. By varying the angle of implantation for each of themultiple implantation stages, for instance, deep shaped openings can beformed with substantially non-vertical sidewalls.

The masking layer in a subsequent procedure is stripped from the layerof silicon-containing material, and the layer of silicon-containingmaterial is then etched with an etching process. The etching processetches portions of a volume of silicon-containing material that are notimplanted with ions to a threshold concentration at a faster rate thanthe etching process etches portions of the volume of silicon-containingmaterial that are implanted with ions up to the threshold concentration.Such an etching process is referred to herein as an etching processwhich is selective to implanted silicon-containing material. The exactconcentration which constitutes the threshold concentration varies inaccordance with the particular etching process and the etching processparameters. Nevertheless, for any such etching process,silicon-containing material implanted with ions beyond the thresholdconcentration is not substantially removed by the etching process whichis selective to implanted silicon-containing material, andsilicon-material implanted to less than the threshold concentration issubstantially removed.

One example of an etching process which is selective to implantedsilicon-containing material is a tetramethyl ammonium hydroxide (TMAH)wet etch. The TMAH wet etch is typically administered as an etchantsolution into which the semiconductor wafer is immersed. Preferredconcentrations of the TMAH wet etch etchant solution comprise from about0.1 weight percent TMAH in a deionized water solution and higher. Morepreferably, a concentration from about 1 to about 10 weight percent TMAHin a solution, and most preferably about 2.5 weight percent TMAH in asolution can be used as the TMAH wet etch etchant solution. The TMAH wetetch is preferably conducted at a temperature in a range from about 5°C. to about 50° C., and more preferably, in a range from about 20° C. toabout 30° C. Most preferably, the TMAH wet etch is conducted at about30° C.

The TMAH wet etch has been found to etch silicon-containing materialimplanted to less than the threshold concentration of ions at least twotimes faster than it etches silicon-containing material that isimplanted to the threshold concentration of ions. Differences in etchrates of 20 to one and 40 to one are easily achievable, and a differencein etch rates of up to 60 to one can be obtained as detailed in U.S.Pat. No. 6,309,975.

When conducting wet etch for polysilicon or other silicon-containingmaterial, the threshold concentration of implanted ions at least topolysilicon is implanted is preferably in a range from about 1×10¹⁵ ionsper cm³ of silicon-containing material to about 1×10²² per cm³ ofsilicon-containing material. More preferably, the thresholdconcentration is in a range from about 5×10¹⁸ ions per cm³ ofsilicon-containing material to about 5×10²⁰ ions per cm³ ofsilicon-containing material. Most preferably, the thresholdconcentration is about 1×10²⁰ ions per cm³ of silicon-containingmaterial. Any relatively unimplanted portion is preferably substantiallyunimplanted with ions.

Common dopants such as boron, arsenic, and phosphorous are suitable foruse as the implanted ions, and in addition, other common dopant ions andeven ions that are not commonly considered to be dopant ions aresatisfactory. For instance, ions can also be successfully used inconjunction with the TMAH wet etch that do not electrically activate orotherwise alter the electrical properties of the silicon-containingmaterial. Examples of such ions are silicon ions and argon ions.

As a result of the etching process which is selective to implantedsilicon-containing material, a selected portion of the polysilicon layerthat is not implanted up to the threshold concentration of ions isetched away to form a shaped opening. Etching process parameters, suchas the duration of the etch, can also be varied to further tailor theresulting etched pattern.

It is also noted that in an alternative embodiment of the presentinvention, an etched structure is formed from a layer ofsilicon-containing material on a semiconductor wafer with an etchingprocess that, converse to the etching process of above, etchessilicon-containing material that is implanted with ions up to athreshold concentration at a substantially faster rate than it etchessilicon-containing material that is not implanted with ions up to thethreshold concentration. In this, the layer of silicon-containingmaterial is etched with an etching process which etches portions of thelayer of silicon-containing material that are implanted with ions up toa threshold concentration at a substantially faster rate than it etchesportions of the layer of silicon-containing material that are notimplanted with ions up to the threshold concentration. Such etchingprocesses are referred to herein as an etching process which isselective to unimplanted silicon-containing material. The concentrationof ions which constitutes the threshold concentration is determined bythe particular etching process which is selective to unimplantedsilicon-containing material that is used and by the selection of the ionimplantation and etching parameters in a manner that will be readilyunderstood from this disclosure by those skilled in the art.

In one embodiment given by way of example, the etching process which isselective to unimplanted silicon-containing material uses an acidicetchant such as commercially available hydrofluoric acid, or it may usea nitric acid etchant solution. Also, a basic etchant, such as KOHetching chemistry can be used, together with a counter-implantation ofthe polysilicon layer.

Representative etch rates of implanted polysilicon illustrate that, ator around a concentration of 1×10²⁰ ions per cm³ of silicon-containingmaterial, the etch rate using the wet etch of the present inventionbegins to fall and continues to fall until an inflection point isreached at or around 1×10²⁰ ions per cm³ of silicon-containing material.Accordingly, with typical implantation and etching parameters, thethreshold concentration is between about 5×10¹⁸ and about 5×10²⁰ ionsper cm³ of silicon-containing material. Of course, the implanted portioncan be implanted with ions in excess of 5×10²⁰ ions per cm³ ofsilicon-containing material, but the excess ions have not been found tosubstantially increase the selectivity to implanted portions of thesilicon-containing material.

FIGS. 2A-2G generally depict a method of forming a portion of a memoryarray in accordance with an embodiment of the invention. FIG. 2A depictsa portion of the memory array after several processing steps haveoccurred. Formation of the structure depicted in FIG. 2A is well knownand will not be detailed herein. In general, FIG. 2A depicts severalstacks 245 of layers that will form word lines of the memory array. Itis noted that as embodiments of the present invention generally areformed or utilized after the word line stacks 245 have been formed, theyare not limited to a particular gate 215, 225 or stack 245 configurationand that the memory array and stacks 245 shown in FIG. 2A are but onepossible embodiment of the present invention.

The stacks 245 of FIG. 2A include a tunnel dielectric 210 formed on asubstrate 205. A floating gate 215 is formed over the tunnel dielectric210. The floating gate 215 is typically formed of a polysilicon layer.An intergate dielectric layer 220 is formed over the floating gate 215.A control gate 225 is formed overlying the dielectric layer 220. Thecontrol gate 225 also forms the word line conductor for the stack 245.In one embodiment, an insulating cap layer 230 is formed overlying thecontrol gate layer 225. The layers are patterned into stacks, as shownin FIG. 2A, and drain regions 235 and source regions 240 are formed inthe substrate 205, such as by implantation or diffusion of dopantmaterials. The drain regions 235 and source regions 240 will have thesame conductivity type and be different from the conductivity type ofthe substrate 205.

In the array of FIG. 2A, the tunnel dielectric 210 is generally asilicon oxide, but may be any dielectric material. Some specificexamples include silicon oxides (SiO/SiO₂), silicon nitrides(SiN/Si₂N/Si₃N₄) and silicon oxynitrides (SiO_(x)N_(y)). For oneembodiment, substrate 205 is a P-type silicon substrate. The floatinggate/first polysilicon layer 215 may be conductively doped. An examplewould be an n-type polysilicon layer. For one embodiment, the dielectriclayer 220 contains the dielectric ONO (oxide-nitride-oxide). Otherdielectric materials may be substituted for the ONO, such as tantalumoxide, barium strontium titanate, silicon nitride and other materialsproviding dielectric properties. The control gate 225 may generally beany conductor, but is typically formed of two conductors (a two layerword line), such as metal over polysilicon or a metal silicide overpolysilicon. In this, the metal layer is generally formed over theentire length of the word line 225, and not just on the exposed portionsof the underlying polysilicon layer. The second or control gatepolysilicon layer 225 may also be conductively doped. In one silicideprocess, generally a layer of refractory metal, e.g., titanium (Ti), isformed overlying the entire structure and followed by an anneal. Themetals of chromium (Cr), cobalt (Co), hafnium (Hf), molybdenum (Mo),niobium (Nb), tantalum (Ta), tungsten (W), vanadium (V) and zirconium(Zr) are generally recognized as other refractory metals. Where therefractory metal is in contact with a silicon layer, such asmonocrystalline silicon or polysilicon, the refractory metal will reactwith the silicon to form a refractory metal silicide. Where therefractory metal is in contact with a layer not containing free silicon,e.g., silicon oxide, silicon nitride, TEOS, etc., the refractory metalwill tend to remain unreacted during the anneal process. The unreactedrefractory metal may then be selectively removed, such as by a wetstrip, leaving behind the refractory metal silicide portions. Thesource/drain regions are also generally more heavily doped than thesubstrate 205. For one embodiment, the substrate 205 has a p-typeconductivity while the drain regions 235 and source regions 240 have ann⁺-type conductivity. While the drain regions 235 and source regions 240were formed after formation of the word line stack for this embodiment,they could also be formed earlier.

Once the stacks of FIG. 2A are formed, a layer of dielectric material275, such as TEOS (tetraethylorthosilicate) or silicon nitride, is thenformed by a blanket deposition process over the patterned word linestacks 245 as shown in FIG. 2B. The layer of dielectric material 275 isutilized to form the dielectric spacers 275 that separate andelectrically insulate the word line stacks 245 from the localinterconnect lines and contacts that are deposited later to connect tothe source regions 235 and drain regions 240.

A mask layer 280 is then formed and patterned over the top of thedielectric spacer material 275. In FIG. 2B, a mask layer 280 is formedoverlying the structure to define areas for removal of the insulatorlayer 275. As one example, the mask layer 280 is a patterned photoresistlayer as is commonly used in semiconductor fabrication. The exposedareas of the insulator layer 275 are then removed in FIG. 2C such as bydry etching or other removal process. This exposes portions of thesubstrate 205 at one or more of the source regions 240 forming trenches.It is noted that trenches for the source regions 240 and contact holesfor the drain regions 235 may be formed either together or separatelyusing one or more separate mask and etch steps.

After the layer of photo resist 280 has been patterned and the exposeddielectric material 275 over the source regions 240 is etched to exposethe source regions 240, the layer of photo resist 280 is then strippedoff and a layer of polysilicon 285 is deposited over the dielectricspacer layer 275. The layer of polysilicon 285 may be conductively dopedor undoped and will contact the exposed cell source regions 240. In oneembodiment, the layer of polysilicon is deposited in a layer thickenough to pinch off in the trenches formed in the layer of dielectricspacer 275, as shown in FIG. 2D. In an alternative embodiment, pinch offof the polysilicon layer is enhanced by decreasing the spacing betweenthe word lines 245 or other array features that define the trenches tobe filled with polysilicon, for example, the spacing of the word lines245 over the source region 240.

A second mask layer 281 is then placed over the top of the dielectricspacer material 275 and patterned to open slots in the mask layer 281over the cell source regions 240. As described in U.S. Pat. No.6,309,975, ions are then implanted into the exposed polysilicon 290, asshown in FIG. 2E. Examples of the implanted ion species include, but arenot limited to boron, arsenic, phosphorous, argon, and silicon. Theimplant depth in one embodiment is set to be approximately one half thethickness of the polysilicon layer 285 to a selected dose level. The iondosage level is typically selected to be in the range of5×10¹⁸/cm³-5×10²⁰/cm³. The second mask layer 281 is then removed and thelayer of polysilicon 285 is wet etched. One such chemical that can beutilized for the wet etch process is dilute TMAH. In one embodiment, theetch is a non-anisotropic etch, etching all surfaces evenly except forthose surfaces that have been ion implanted. The ion implantationgenerates a wet etch selectivity (a slower etch rate) between theimplanted polysilicon film 290 and non-implanted polysilicon film 285.This allows the non-implanted polysilicon 285 to be etched away andleave the implanted polysilicon 290 local interconnects coupled to thesource region 240, as shown in FIG. 2F. In one embodiment, the secondlayer of photo resist is patterned and the polysilicon layer 285 is ionimplanted such that a “T” shaped or a “Y” shaped local interconnect isformed in the trench that partially covers the corners of the adjacentword line stack 245. This allows the formed local interconnect toadvantageously protect the spacer dielectric 275 on corners of the wordline stacks 245 from potential thinning due to further processing and/oretching and has the additional beneficial effect of decreasing theresistance of the resulting local interconnect 290 by providing a largercross sectional area. In addition, the T or Y shape also improves theedge definition of the local interconnect and limits undercutting of thelocal interconnect during etching. Contact formation to the localinterconnect, and current carrying capacity of the interconnect line arepromoted, and interconnect resistance is reduced by this interconnectshape. It is also noted that the word line cap 230 formed in oneembodiment of the present invention increases insulation available onthe top of the word line stack 245. This helps improve the insulation ofthe word line 245 and mitigates any stair step formation in the spacerinsulation due to etching during the formation of the localinterconnect.

Once the local interconnects 290 have been formed, a layer of insulatingdielectric 265 such as a doped silicate glass, is deposited. Examples ofdoped silicate glasses include as BSG (borosilicate glass), PSG(phosphosilicate glass) and BPSG (borophosphosilicate glass). After thelayer of insulating dielectric 265 is deposited, bit lines 295 and drainregion contacts 293 are formed, and word lines 245 and source localinterconnects 290 connected using, e.g., standard contact andmetalization process steps, finishing the forming of the memory arrayand leaving the structure depicted in FIG. 2G.

In embodiments of the invention, by utilizing a low resistancepolysilicon local interconnect the source interconnect 290 can extendover a much larger group of memory cells in addition to allowing thereduction in word line pitch. This configuration can facilitate arraysource interconnects extending 32 columns or more without coupling to anarray ground. In addition, by utilizing a shallow junction for thesource region 240, a smaller channel can be utilized in the memoryarray, thus facilitating a reduction in device size and a reduction inpitch. As described herein, a memory cell is a single floating-gatetransistor formed of a word line 225, drain region 235, source region240 and a channel region defined by the area interposed between thedrain region 235 and source region 240. It is also noted that theformation of bit line contacts utilizing the techniques disclosedherein. However, in forming bit line contacts, the area of dielectricand polysilicon exposed over the drain region will typically be in theform of a contact hole rather than a trench.

FIG. 3 is a schematic of a portion of a non-volatile memory array 300 asa portion of a memory device in accordance with one embodiment of theinvention. The detail of memory array 300 is provided to betterunderstand the various embodiments of the invention. The memory array300 includes local interconnect lines formed in accordance with anembodiment of the invention.

The layout of FIG. 3 corresponds to one example of a NOR flasharchitecture. However, other types of memory arrays can benefit fromembodiments of the invention. As one example, word lines, drain contactsand source interconnects can be fabricated in accordance with theinvention for NAND flash architectures as well, although only one draincontact is required per string and only one source interconnect isrequired per block. Accordingly, the invention is not limited to thespecific layout described with reference to FIG. 3.

As shown in FIG. 3, the memory block 300 includes word lines 302 andintersecting local bit lines 304. For ease of addressing in the digitalenvironment, the number of word lines 302 and the number of bit lines304 are each some power of two, e.g., 256 word lines 302 by 4,096 bitlines 304. The local bit lines 304 may be selectively coupled to globalbit lines (not shown) for coupling to sense amplifiers (not shown inFIG. 3).

Floating-gate transistors 306 are located at each intersection of a wordline 302 and a local bit line 304. The floating-gate transistors 306represent the non-volatile memory cells for storage of data. Typicalconstruction of such floating-gate transistors 306 include a source 308and a drain 310 constructed from an n⁺-type material of high impurityconcentration formed in a P-type semiconductor substrate of low impurityconcentration, a channel region formed between the source and drain, afloating gate 312, and a control gate 314. Floating gate 312 is isolatedfrom the channel region by a tunneling dielectric and from the controlgate 314 by an intergate dielectric. Floating-gate transistors 306having their control gates 314 coupled to a word line 302 typicallyshare a common source 308 depicted as array source interconnect 316. Asshown in FIG. 3, floating-gate transistors 306 coupled to two adjacentword lines 302 may share the same array source interconnect 316.Floating-gate transistors 306 have their drains coupled to a local bitline 304. A column of the floating-gate transistors 306 are thosetransistors commonly coupled to a given local bit line 304. A row of thefloating-gate transistors 306 are those transistors commonly coupled toa given word line 302.

The array source interconnects 316 may be coupled to a metal or otherhighly conductive line to provide a shared path to a ground potentialnode. The array ground 318 serves as this shared path. For oneembodiment, a connection between an array source interconnect 316 andthe array ground 318 occurs only once for each row of memory cells 306.Typical memory devices may require a contact between an array sourceinterconnect and an array ground every 16 columns.

FIG. 4 is a functional block diagram of a basic flash memory device 400that is coupled to a processor 401. The memory device 400 and theprocessor 401 may form part of an electronic system. The memory device400 has been simplified to focus on features of the memory that arehelpful in understanding the present invention. The memory device 400includes an array of non-volatile memory cells 402. The memory array 402includes word lines formed in accordance with an embodiment of theinvention.

Each memory cell is located at an intersection of a word line and alocal bit line. The memory array 402 is arranged in rows and columns,with the rows arranged in blocks. A memory block is some discreteportion of the memory array 402. Individual word lines generally extendto only one memory block while bit lines may extend to multiple memoryblocks. The memory cells generally can be erased in blocks. Data,however, may be stored in the memory array 402 separate from the blockstructure.

The memory array 402 is arranged in a plurality of addressable banks. Inone embodiment, the memory contains four memory banks 404, 406, 408 and410. Each memory bank contains addressable sectors of memory cells. Thedata stored in the memory can be accessed using externally providedlocation addresses received by address register 412 from processor 401on address lines 413. The addresses are decoded using row addressmultiplexer circuitry 414. The addresses are also decoded using bankcontrol logic 416 and row address latch and decode circuitry 418.

To access an appropriate column of the memory, column address counterand latch circuitry 420 couples the received addresses to column decodecircuitry 422. Circuit 424 provides input/output gating, data masklogic, read data latch circuitry and write driver circuitry. Data isinput through data input registers 426 and output through data outputregisters 428. This bidirectional data flow occurs over data (DQ) lines443.

Command execution logic 430 is provided to control the basic operationsof the memory device including memory read operations. A state machine432 is also provided to control specific operations performed on thememory arrays and cells. A high voltage switch and pump circuit 445 isprovided to supply higher voltages during erase and write operations. Astatus register 434 and an identification register 436 can also beprovided to output data.

The memory device 400 can be coupled to an external memory controller,or processor 401, to receive access commands such as read, write anderase command. Other memory commands can be provided, but are notnecessary to understand the present invention and are therefore notoutlined herein. The memory device 400 includes power supply inputs Vssand Vcc to receive lower and upper voltage supply potentials.

As stated above, the flash memory device 401 has been simplified tofacilitate a basic understanding of the features of the memory device. Amore detailed understanding of flash memories and memories in general isknown to those skilled in the art. As is well known, such memory devices401 may be fabricated as integrated circuits on a semiconductorsubstrate.

CONCLUSION

Method and apparatus have been described to facilitate forming of lowresistance polysilicon local interconnects that allow a smaller memoryarray feature size and therefore facilitate forming arrays of a denserarray format. Embodiments of the present invention are formed utilizinga wet etch process that has a high selectivity, allowing the depositionand etching of polysilicon local interconnects to source and drainregions of array transistors. In addition, by forming localinterconnects and contacts to the source regions of array elements witha high selectivity etch the size of the area dedicated to eachinterconnect line is reduced, thus allowing the use of a smaller pitch,i.e., a smaller spacing between adjacent word lines. By providing for alocal interconnect of polysilicon, a smaller source region and/or drainregion can also be utilized, further decreasing the required word linespacing. Low resistance polysilicon local source interconnects can alsocouple to an increased number of memory cells, thereby reducing thenumber of contacts made to an array ground.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement that is calculated to achieve the same purpose maybe substituted for the specific embodiments shown. Many adaptations ofthe invention will be apparent to those of ordinary skill in the art.Accordingly, this application is intended to cover any adaptations orvariations of the invention. It is manifestly intended that thisinvention be limited only by the following claims and equivalentsthereof.

1. A floating-gate memory cell, comprising: a tunnel dielectric layerformed overlying a semiconductor substrate; a drain region formed in asemiconductor substrate adjacent a first side of the tunnel dielectriclayer; a source region formed in a semiconductor substrate adjacent asecond side of the tunnel dielectric layer; a floating-gate layer formedoverlying the tunnel dielectric layer; an intergate dielectric layerformed overlying the floating-gate layer; a control-gate layer formedoverlying the intergate dielectric layer; a first contact coupled to thesource region; and wherein the first contact comprises a polysiliconlocal interconnect line with an ion implanted top layer formed in atrench shaped region in an overlying bulk insulator layer.
 2. Thefloating-gate memory cell of claim 1, further comprising: a secondcontact coupled to the drain region, wherein the second contactcomprises a polysilicon layer with an ion implanted top layer.
 3. Thefloating-gate memory cell of claim 2, wherein the second contactcomprises a second polysilicon local interconnect line with an ionimplanted top layer formed in a second trench shaped region in theoverlying bulk insulator layer.
 4. The floating-gate memory cell ofclaim 3, wherein the second polysilicon local interconnect line of thesecond contact has a “T” or “Y” shaped cross sectional area.
 5. Thefloating-gate memory cell of claim 1, wherein the control-gate layercomprises a silicide layer in contact with an underlying polysiliconlayer.
 6. The floating-gate memory cell of claim 1, further comprising:a word line cap dielectric layer formed overlying the control-gatelayer.
 7. The floating-gate memory cell of claim 1, wherein there is nointerposing dielectric layer between the control-gate layer and theoverlying bulk insulator layer.
 8. The floating-gate memory cell ofclaim 1, wherein the polysilicon local interconnect line of the firstcontact has a “T” or “Y” shaped cross sectional area.
 9. Thefloating-gate memory cell of claim 1, wherein the polysilicon localinterconnect line is conductively doped.
 10. The floating-gate memorycell of claim 1, wherein the polysilicon local interconnect line of thefirst contact is formed by: forming a first mask layer over theoverlying bulk insulator layer; patterning the first mask layer toexpose a portion of the overlying bulk insulator over at least thesource region; removing a portion of the exposed portion of theoverlying bulk insulator to form the trench shaped region and expose thesource region; removing the first mask layer; forming a layer ofpolysilicon overlying the overlying bulk insulator and trench shapedregion and in contact with the exposed source region; forming a secondmask layer overlying the layer of polysilicon; patterning the secondmask layer to expose a portion of the layer of polysilicon over at leastthe trench shaped region; implanting ions in the exposed portion of thelayer of polysilicon, thereby forming an implanted portion of the layerof polysilicon and an non-implanted portion of the layer of polysilicon;removing the second mask layer; and selectively etching the layer ofpolysilicon to preferentially remove the non-implanted portion, therebyforming the polysilicon local interconnect line in the trench shapedregion.
 11. The floating-gate memory cell of claim 10, wherein forming afirst and/or second mask layer further comprises forming a first and/orsecond mask layer with a photoresist.
 12. The floating-gate memory cellof claim 10, wherein selectively etching the layer of polysilicon topreferentially remove the non-implanted portion, thereby forming thepolysilicon local interconnect line further comprises selectively wetetching the layer of polysilicon to preferentially remove thenon-implanted portion, thereby forming the polysilicon localinterconnect line.
 13. The floating-gate memory cell of claim 12,wherein wet etching further comprises wet etching with TMAH.
 14. Thefloating-gate memory cell of claim 12, wherein wet etching furthercomprises wet etching with KOH.
 15. A floating-gate memory cell,comprising: a tunnel dielectric layer formed overlying a semiconductorsubstrate; a drain region formed in a semiconductor substrate adjacent afirst side of the tunnel dielectric layer; a source region formed in asemiconductor substrate adjacent a second side of the tunnel dielectriclayer; a floating-gate layer formed overlying the tunnel dielectriclayer; an intergate dielectric layer formed overlying the floating-gatelayer; a control-gate layer formed overlying the intergate dielectriclayer; a first contact coupled to the source region, wherein the firstcontact comprises a first polysilicon local interconnect line with anion implanted top layer formed in a trench shaped region in an overlyingbulk insulator layer; and a second contact coupled to the drain region,wherein the second contact comprises a second polysilicon localinterconnect line with an ion implanted top layer.
 16. The memory cellof claim 15, wherein the control-gate layer comprises a silicide layerin contact with an underlying polysilicon layer.
 17. The memory cell ofclaim 15, further comprising: a word line cap dielectric layer formedoverlying the control-gate layer.
 18. The memory cell of claim 15,wherein there is no interposing dielectric layer between thecontrol-gate layer and the overlying bulk insulator layer.
 19. Thememory cell of claim 15, wherein the polysilicon local interconnect lineof the first contact has a “T” or “Y” shaped cross sectional area. 20.The memory cell of claim 15, wherein the second polysilicon localinterconnect line of the second contact has a “T” or “Y” shaped crosssectional area and is formed in a second trench shaped region in theoverlying bulk insulator layer.
 21. The floating-gate memory cell ofclaim 15, wherein the first and second polysilicon local interconnectlines are conductively doped.